Sr Staff Digital Verification Engineer

I am currently looking for an outstanding DV engineer to strengthen our team in the Milan area.

My client offers a whole array of benefits including; a competitive salary package (10-15% above current salary), a hybrid working model, fuel vouchers, meal vouchers, and a relocation package.
 

Your responsibilities will be:

• Verification of integrated mixed signal and digital blocks and CMOS IC’s
• Creation of verification plans for complex mixed signal or digital devices
• Development of verification environment and ensure proper verification coverage for enabling bug free silicon manufacturing.
• Creation of DV test cases and debugging of simulation results

Requirements you must posses:

• University degree in Electronics or related
• 6+ years experience in digital design/verification with hands-on experience on relevant design/simulation tools
• Knowledge of design verification methodologies, tools and languages (UVM, SystemVerilog, assertions …)
• Analytical mind for solving complex problems and debugging design issues popping up in simulations
• Team oriented, committed to deadlines and development discipline
• Communication skills and proficiency in English
• Some knowledge in other areas of Digital Design are considered as a plus, such as some knowledge of RTL design with HDL (Verilog/VHDL) for integrated devices, knowledge of DFT and test-pattern generation
• • Experience in analog blocks modeling