Senior DDR Validation Engineer | MRL Consulting

Senior DDR Validation Engineer

We are recruiting on behalf of an innovative technology company for an experienced Senior DDR Validation Engineer to support the development and validation of advanced modem platforms and satellite communication systems.

Key Responsibilities

• Validate DDR3/DDR4 interfaces and perform system bring-up.

• Develop and execute DDR validation plans, including timing, voltage, frequency and temperature margin analysis.

• Debug memory training, calibration and initialization issues.

• Support FPGA development and hardware/software co-validation.

• Validate high-speed interfaces including DDR, PCIe and USB.

• Perform signal integrity analysis and automate testing using Python and C/C++.

• Collaborate with cross-functional engineering teams to deliver robust, production-ready solutions.

Requirements

• Degree in Electrical Engineering, Computer Engineering or a related discipline.

• 5+ years' experience in DDR validation, FPGA development or high-speed digital systems.

• Strong knowledge of DDR3/DDR4, JEDEC standards and memory controller architecture.

• Experience with FPGA bring-up, Python, C/C++, Git and automated regression frameworks.

• Hands-on experience using lab equipment such as oscilloscopes and JTAG debuggers.

• Excellent analytical, debugging and communication skills.

This is an excellent opportunity to join a cutting-edge engineering environment, working on advanced communications technology alongside multidisciplinary teams.