ASIC Design Engineer - PCle

7279
  • Competitive
  • United States
  • Semiconductor
  • Permanent
We're currently on the lookout for an adept ASIC Design Engineer specializing in PCIe protocol, particularly its physical layer intricacies. The ideal candidate will boast a wealth of system-level expertise in PCIe, alongside hands-on proficiency in silicon bring-up and debugging within the PCIe domain. Extensive experience in ASIC design, coupled with mastery in Verilog and SystemVerilog, is a must. The role necessitates a deep understanding of Serializer/Deserializer (SerDes) technology and its application in high-speed data transmission.
Responsibilities:
PCIe System Mastery:
  • Thorough understanding and practical experience in PCIe system architecture, particularly in physical layer design and specification.
  • Ensure adherence to PCIe specifications, encompassing PIPE interface, LTSSM, 8b/10b and 128b/130b encoding, EIEOS intervals, equalization, and electrical idle conditions.
  • Profound comprehension of PCIe retimer specification.
  • Lead silicon bring-up endeavors, troubleshooting, and resolving PCIe-related issues.
ASIC Design and SerDes Proficiency :
  • Conceptualize, implement, and validate ASIC components, focusing on PCIe physical layer prerequisites.
  • Leverage Verilog and SystemVerilog for development, ensuring alignment with performance and design standards.
  • Extensive understanding of SerDes technology, encompassing its functionality, design intricacies, and integration into high-speed communication interfaces.
Requirements:
  • PhD with 10+ years, or MSEE with 13+ years, or BSEE with 15+ years of equivalent experience in ASIC design and verification.
  • Proficiency in relevant languages for ASIC development, including Verilog, SystemVerilog, Unix/Perl Scripting, or Python.
  • Complete understanding of PCIe protocol, with hands-on experience in PCIe system architecture, particularly in physical layer design and specification.
  • Demonstrated expertise in silicon bring-up and debugging involving PCIe protocol.
  • Strong grasp of high-speed digital circuit design and RTL simulation and synthesis.
  • Analytical acumen, adept problem-solving skills, and practical lab debugging experience.
  • In-depth knowledge of low-power design, test design, and manufacturing design principles.
  • Self-motivated with excellent communication skills and the ability to thrive in a team environment.
  • Strong organizational skills with a commitment to issue resolution and closure.
  • Ability to collaborate with remote teams across different time zones.
  • Detail-oriented with robust multitasking capabilities and exceptional problem-solving prowess.

 
Julian Bahrami Senior Account Manager

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