Design Verification Engineer

Design Verification Engineer
The engineer will work closely with the design team, and be responsible for all aspects of verifying that the digital core is fully functionally compliant with the specification at the top level. They will be responsible for the verification environment and be able to develop models for analog.

Primary Job Responsibilities

• Managing the digital verification environment for the design
• Setting methodologies and guidelines for digital verification on the project
• Reviewing the internal/customer specification and generating a full test plan and environment to confirm compliance
• Reviewing RTL to debug and understand any issues, and propose solutions
• Working closely with the design team to resolve any issues
• Design of some digital sub-blocks

Qualifications

• BSEE +5 years or MSEE +3 years of relevant experience. At least 3 years of digital verification, including test writing and verification of several products
• Experience with using the Cadence Virtuoso software and AMS simulation environment
• Comfortable with exploring the analog schematic hierarchy in Cadence
• Able to write and debug System Verilog models. Previous real number modelling experience a plus
• Can create thorough block and system level SV assertions
• Experience in debugging simulation issues and bug identification
• A good understanding of UVM, and the ability to import an environment from an existing project and improve upon it
• Strong scripting skills is a highly desirable (csh, Python and TCL)
• Able to work well in a remote team environment, including good communication and inter-personal skills
• Self-starter able to manage his/her own time effectively
• #LI-JB2