DRAM Design Engineer – Next-Generation HBM / Memory Architecture
9830
Posted: 30/09/2026
- Competitive
- United States
- Semiconductor
- Permanent
DRAM Design Engineer – Next-Generation HBM / Memory Architecture
Level: Member of Technical Staff (MTS) through Distinguished Member of Technical Staff (DMTS), depending on experience
Location: United States
Employment Type: Full-time
About the Role
We are working with a leading semiconductor technology organization developing next-generation memory solutions for high-performance computing, artificial intelligence, and other demanding data-intensive applications.
We are seeking an experienced DRAM Design Engineer to join a highly technical architecture and circuit design team focused on the development and optimization of advanced, high-bandwidth memory architectures.
This is an opportunity to work at the intersection of DRAM circuit design, memory architecture and next-generation stacked memory, helping define technologies where performance, power efficiency and silicon area are critical.
The successful candidate will be involved in identifying architectural opportunities, developing circuit-level solutions, modelling and simulating designs, and working closely with teams across architecture, circuit design, layout, verification and silicon development.
The level of appointment can range from Member of Technical Staff (MTS) / Senior MTS to Distinguished Member of Technical Staff (DMTS), depending on the candidate's technical depth, experience and demonstrated impact.
Key Responsibilities
Required Experience
Preferred Experience
Experience in one or more of the following would be advantageous:
Education & Experience
Senior / Distinguished-Level Opportunities
Candidates operating at Senior MTS, Principal, Senior Principal or DMTS level are encouraged to apply.
At the higher levels, we are particularly interested in engineers who can demonstrate:
Why Join?
This is an opportunity to work on next-generation memory technology supporting rapidly evolving AI and high-performance computing applications, alongside experienced engineers working on some of the most challenging problems in semiconductor memory design.
The role offers scope to make a significant technical contribution, with opportunities ranging from hands-on circuit development through to architectural and technical leadership.
If you have deep DRAM circuit design experience and are interested in working on next-generation high-bandwidth memory architecture, we would be interested in speaking with you.
#LI-JA1
Level: Member of Technical Staff (MTS) through Distinguished Member of Technical Staff (DMTS), depending on experience
Location: United States
Employment Type: Full-time
About the Role
We are working with a leading semiconductor technology organization developing next-generation memory solutions for high-performance computing, artificial intelligence, and other demanding data-intensive applications.
We are seeking an experienced DRAM Design Engineer to join a highly technical architecture and circuit design team focused on the development and optimization of advanced, high-bandwidth memory architectures.
This is an opportunity to work at the intersection of DRAM circuit design, memory architecture and next-generation stacked memory, helping define technologies where performance, power efficiency and silicon area are critical.
The successful candidate will be involved in identifying architectural opportunities, developing circuit-level solutions, modelling and simulating designs, and working closely with teams across architecture, circuit design, layout, verification and silicon development.
The level of appointment can range from Member of Technical Staff (MTS) / Senior MTS to Distinguished Member of Technical Staff (DMTS), depending on the candidate's technical depth, experience and demonstrated impact.
Key Responsibilities
- Develop and evaluate novel DRAM circuit architectures for next-generation high-bandwidth and high-performance memory applications.
- Identify circuit and architectural bottlenecks and develop data-driven solutions to improve performance, power and area (PPA).
- Translate architectural concepts into schematic-level circuit designs and validate them through SPICE simulation and detailed trade-off analysis.
- Work across different areas of DRAM design, potentially including:
- Memory cell arrays
- Sense amplifiers
- Row and column decoding
- DRAM peripheral circuitry
- I/O circuits
- Power distribution and related circuitry
- Collaborate with physical design and layout teams on floor planning and implementation studies.
- Contribute to design-for-test, design-for-yield and manufacturability considerations.
- Develop technical specifications, architecture documentation and design methodologies.
- Work closely with engineers across memory architecture, circuit design, physical design, systems and silicon development.
- Influence technical direction through rigorous simulation, analysis and engineering data.
- At senior and distinguished levels, provide technical leadership on complex architecture and design problems and help shape longer-term memory technology roadmaps.
Required Experience
- Strong experience in mixed signal / custom IC design, including analog circuit design and relevant synthesis or implementation flows.
- Demonstrable experience designing DRAM circuits or memory architecture.
- Experience in one or more key DRAM design areas such as cell arrays, sense amplifiers, decoders, peripheral circuitry, I/O or power delivery.
- Strong experience with SPICE-based circuit simulation and analysis.
- Ability to evaluate circuit architectures through quantitative performance, power and area trade-offs.
- Strong technical communication skills, with the ability to present complex engineering analysis and influence technical decisions.
Preferred Experience
Experience in one or more of the following would be advantageous:
- HBM / High Bandwidth Memory
- 2.5D or 3D-stacked memory architectures
- Advanced DRAM or other novel memory technologies
- High-speed memory interfaces
- Semiconductor device physics
- Custom analog / mixed-signal circuit design
- Python, Perl or other engineering scripting languages
- Verilog or another hardware description language
- Design-for-test and design-for-yield methodologies
- Semiconductor product development through tape-out and silicon validation
Education & Experience
- Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science or a related technical discipline, or equivalent industry experience.
- Significant professional experience in DRAM, memory circuit design or semiconductor IC development.
- For senior and distinguished-level candidates, a substantial track record of delivering complex memory designs and influencing architecture or technology direction is expected.
Senior / Distinguished-Level Opportunities
Candidates operating at Senior MTS, Principal, Senior Principal or DMTS level are encouraged to apply.
At the higher levels, we are particularly interested in engineers who can demonstrate:
- Deep technical expertise in DRAM and/or advanced memory architecture.
- Ownership of complex circuit or architectural problems from concept through implementation.
- A track record of solving difficult PPA, performance, reliability or scalability challenges.
- Technical leadership across multiple engineering disciplines.
- The ability to define new approaches rather than simply execute established designs.
- Strong influence within technically complex semiconductor development environments.
Why Join?
This is an opportunity to work on next-generation memory technology supporting rapidly evolving AI and high-performance computing applications, alongside experienced engineers working on some of the most challenging problems in semiconductor memory design.
The role offers scope to make a significant technical contribution, with opportunities ranging from hands-on circuit development through to architectural and technical leadership.
If you have deep DRAM circuit design experience and are interested in working on next-generation high-bandwidth memory architecture, we would be interested in speaking with you.
#LI-JA1
Jack Adams
Senior Delivery Consultant