Principal PCIe Subsytem RTL Lead
9696
Posted: 17/08/2026
- Competitive
- California, United States
- Semiconductor
- Permanent
We are looking for a Principal PCIe Sub-system Front-end RTL Lead to drive the development of next-generation chiplet-based SoCs for high-performance compute and AI applications.
What You’ll Do
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Own the PCIe subsystem microarchitecture from the PHY interface through the MAC and Transaction Layer, defining block boundaries, data paths, and control interfaces.
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Lead the integration of third-party PCIe controller and PHY hard IP, including wrapper RTL, mode selection, telemetry hooks, and bridging logic to the chiplet’s internal fabric.
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Define and implement bifurcation and lane-configuration logic, ensuring all supported lane-width configurations operate correctly across operating modes.
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Specify and drive implementation of the Transaction Layer pipeline, including TLP reception, integrity checking, header classification, routing decisions, and downstream handoff.
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Own the Virtual Channel and flow-control architecture, including arbitration, traffic prioritization, and back-pressure handling.
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Define subsystem integration interfaces, including TLP-to-flit adaptation, flow-control mapping, and error handling at the subsystem boundary.
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Collaborate with firmware teams to define the PCIe register map, mode-selection interfaces, and runtime telemetry structures exposed to the on-chip management processor.
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Work with Physical Design to achieve timing closure across the PCIe subsystem, including MAC-PHY interface timing, reset sequencing, and floorplan constraints.
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Own the PCIe performance budget for each operating mode, including bandwidth efficiency, Transaction Layer latency, and error-recovery overhead.
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Define the PCIe power-management architecture, including link-state transitions, ASPM policy, and integration with chiplet-level power-management schemes.
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Lead PCIe silicon bring-up planning, including bring-up sequences, debug instrumentation, loopback modes, and production-readiness criteria.
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Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural direction and conducting RTL reviews.
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Partner with the DV team to define the PCIe UVM verification strategy, coverage model, and protocol-checker requirements.
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Serve as the technical point of contact for PCIe-related integration and interoperability questions.
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Author and maintain the PCIe subsystem microarchitecture specification throughout RTL implementation, verification, and sign-off.
Julian Bahrami
Senior Consultant